Digital Design Verification
hace 3 meses
**Job Code**:#112**
***
**INTERNSHIP**:
**Digital Design Verification**
**Location(s)**:
- Córdoba, Argentina
**Overview**:
**Responsibilities**:
- Cover basic concepts of digital verification, including structure of a Verification Environment, hardware design simulation, HDD (Hardware Driven Design) flow, and coverage types.
- Cover basic concepts of SystemVerilog such as data types, control structures (if,for,while), functions, procedures, macros, and classes.
- Creation of a basic testbench in SystemVerilog, involving fundamental programming techniques.
- Learn about the UVM methodology, covering classes, components, and architecture, with the ultimate goal being the creation of a UVM testbench.
- Introduction to concepts of Formal Verification and Functional Verification.
- Use verification tools to run tests, initiate regressions, and analyze coverage in the verification process.
- Introduction to PyUVM and development of a PyUVM testbench.
**Requirements**:
- Currently studying last year of Electronic Engineering and related degrees.
- Familiarity with RTL (preferred Verilog), C, and scripting (preferred Python).
- Familiarity with revision control systems (i.e. SVN, GIT)
- Energetic contributor with the ability to learn fast and communicate (English) effectively
- Experience with Xilinx devices/tools and Linux will be valued.
- indie_ _Semiconductor and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law._
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