High-Performance Systems Engineering Manager

hace 5 días

Buenos Aires, Buenos Aires C.F., Argentina Cadence Design Systems, Inc. A tiempo completo

Cadence Design Systems, Inc. is a leading provider of electronic design automation (EDA) software and intellectual property (IP). We hire and develop leaders and innovators who want to make an impact on the world of technology.

The Compute Systems Group (CSG) at Cadence develops and licenses IP for system designs, including CPUs and high-performance DSPs, DDR and IO controllers, hardware accelerators, and subsystems. Our IP designs are used by most top semiconductor vendors today, and our customers ship billions of chips annually using our components.

We're seeking an experienced SoC Design Manager to lead a new team for CSG systems. In this role, you'll manage a team of hardware design engineers to develop and validate reference systems for Computer Vision, Machine Learning, Radar, Automotive, and other high-performance applications. This is a technically rewarding role with high visibility within the organization.

As a hands-on management role, technical expertise in implementing SoC and compute-based systems is required. You'll work closely with compute and interface IP development engineering, building designs to demonstrate the capabilities of CSG subsystems and components.

Key Responsibilities

  • Build, manage, and mentor a team of hardware design engineers, providing guidance, support, and opportunities for professional growth.
  • Collaborate with cross-functional teams, including software and IP teams, to ensure seamless integration and alignment on hardware and software components.
  • Develop reference designs, collateral, and training material for CSG system customers. Build and train an organization to support users.
  • Identify and implement best practices in hardware design, testing, and validation to improve efficiency and reliability. Stay up-to-date with latest industry trends, technologies, and design methodologies, and incorporate them into team's workflows.

Requirements

  • At least 4 years of experience in managing ASIC design, integration, or verification teams.
  • Expertise in any of the following domains: processor design, on-chip communication and interconnects, high-speed interfaces, or chiplets.
  • Expertise in Verilog/System Verilog for coding and verification.
  • Proficiency in RTL design techniques, including synthesis, timing closure, and verification.
  • Experience in using UVM for functional verification of ASIC designs.
  • Experience with EDA tools like Cadence and Synopsys for design simulation and verification.
  • Extensive experience with FPGA emulation, design tools, and verification.
  • Bachelor's degree in EE/CS with 10+ years work experience, or Master's degree in EE/CS with 8+ years experience.
  • Somewhat frequent travel may be required.

Compensation: $180,000 - $220,000 per annum, depending on experience.

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