Frontend Digital Implementation Lead

hace 2 meses

San Nicolás de los Arroyos, Buenos Aires, Argentina Cadence Design Systems, Inc. A tiempo completo

About Cadence Design Systems, Inc.

Cadence Design Systems, Inc. is a leader in the development of electronic design automation (EDA) software and hardware used to design and verify electronic systems.

Job Summary

We are seeking a highly skilled Digital Design Solutions Principal to join our team. As a key member of our Frontend Digital Implementation team, you will be responsible for leading technical campaigns and strategies in the Frontend digital implementation space.

Key Responsibilities

  • Hands-on work with customers in the areas of Frontend Digital Design Implementation, including Synthesis, DFT, and Logical Equivalence, Low Power, Power Characterization.
  • Lead technical campaigns and strategies in the Frontend digital implementation space.
  • Aggressively push Power, Performance, and Area (PPA) improvements.
  • Deliver technical presentations and lead discussions internally and with customers.
  • Work closely with R&D to enhance the tools and methodologies to meet and exceed customer requirements with high quality.
  • Support execution on critical customer flagship product tape outs.
  • Amend and augment the flow as needed using Tcl and/or other programming skills to meet objectives and improve results/flows.

Requirements

  • MS degree in Computer Science/Engineering, Electrical Engineering, or related field, plus 8+ years industry experience.
  • Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis.
  • Prior experience with IC digital implementation flows and front-end EDA tools, including Synthesis, DFT, and Logical Equivalence Checking, Low Power, Power characterization.
  • Expert in RTL Synthesis and ability to rewrite RTL to accomplish improved PPA.
  • Experience in scripting in Perl/Tcl/Python to automate and implement process improvement.
  • Experience with advanced technology nodes, including Sub 5nm and below.
  • Develop, debug, and optimize various aspects of design flows for SoCs to achieve best Power, Performance, and Area (PPA).
  • Strong customer-facing communication and problem-solving skills.
  • Strong personal drive for continuous learning and expanding professional skillsets.
  • Strong verbal, written, and customer communication skills.

Preferred Qualifications

  • Good hands-on experience of Floorplanning, Place and Route, Timing analysis and Sign-off, preferable with CDNS tools suite.
  • Prior experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, and/or Voltus is highly desired.

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